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There’s an interesting hardware segment when you want to realize a digital logic circuit and don’t want a full-blown microcontroller — do away with stacks, operating systems, and don’t want the most basic discrete logic gates action, à la DIL14. This is where the SPLDs (PLA and PAL), CPLDs, and FPGAs live and come into action. They’re super fast and clean, relatively easy to understand and implement compared to their siblings (micros, cpus).

A quick glanze at digital logic; the output of a logic function is based on the desired behavior dictated by the stimuli applied to the inputs, meaning all possible input combinations can be set to have a specific output. The input and output logic is usually arranged in a truth-table and the can be minimized by method of boolean algebra or Karnaugh-map. The point of minimization is to use as little hardware as necessary and consecutively improve operation speed and power consumption. An example of a three-variable function and a very basic realization.

• PLA – Programmable Logic Array, can realize sum-of-product functions by implementing them using a set of input inverters, AND-gates and OR-gates. Two AND- and OR-planes can be programmed to realize a function. PLAs are used in very basic circuits, preceded by PAL because of lower cost.
  • Diagram of the PLA structure and an example
• PAL – Programmable Array Logic, is a improved PLA where the OR-plane is fixed and only the AND-plane is programmable, thus reducing manufacturing cost but is less flexible (less inputs to OR-plane leads to more PAL circuits needed to realize a function).
  • Schematic view of a PAL

PLA and PAL devices are suitable for simple applications and small circuits, constrained by the number of inputs and outputs physically possible to fit on a chip, as there’s no internal interconnection possibility.

The functions are normally not reduced by hand, but by CAD-programs minimizing and producing functions suitable for the design of a particular device. The final programming file contains the details of which interconnection- and cell-switches to turn on (denoted by X in the diagrams).

The programmable switch is a special transistor that retains it’s state if a higher-than-normal voltage pulse is applied, normally 12V. These switches are also known as PROM and EPROM if they’re re-progammable e.g. erasable.

• CPLD – Complex Programmable Logic Device, contains a number of individual cells similar to PALs, each with programmable AND- and OR-planes. Interconnection wires makes it possible to connect output of one cell to the input of another. The X switches for cells and interconnectivity are programmed in the same manner as SPLDs (PLAs and PALs).
  • Diagram of the CPLD structure and PAL-like block
• FPGA – Field Programmable Gate Arrays, trumps them all. It is quite different from the before-mentioned types. Instead of planes, the structure consists of logic blocks and interconnection switches. The logic blocks can vary but the most commonly used type is a lookup table, or LUT. Up to 32 cells can be used to hold logic values, controlled by log2(cells) inputs, i.e. 32 cells will require 5 inputs. The stored cell values produce the output of the logic block. Making it possible to realize any function as long as the function is minimized into usable “chunks” to fit the available LUT inputs, a process called multilevel synthesis. FPGAs are used where very fast and parallel processing is needed; signal processing, video encoding, wireless mobile communication.
  • General structure of a FPGA and an example
• Custom chips – The holy grail. If a function is finalized for an application, it can be manufactured directly on a chip to lower the area of unused space on a chip and at the same time lower manufacturing cost. And more importantly a reduction in the speed of operation and power consumption. Used for mass production of chips; microprocessors, memory chips, audio codecs, network interface controllers, broadband access controllers, card reader controllers.
  • Custom chip diagram and an example

The size of a device is measured in how many equivalent two-input NAND gates it can represent. A SPLD or CPLD typically has about 20 equivalent gates per macrocell, meaning a PAL with 8 macrocells is equivalent to 160 gates, and CPLD with 500 macrocells 10 000 gates. A FPGAs can, as of March 2011, range from 1000 to 2 million equivalent gates.

Images courtesy of McGraw-Hill and Fundamentals of Digital Logic with VHDL Design, a highly recommended book.